Microprocessor connects to peripherals using bus. Lately, to speed up the process, multiple topologies and peripherals have been fabricated on same chip which contains the processor. This is called system on Chip or SoC.
But, Still the fundamental problem of communication between the mup and peripherals still used to cause a bottleneck.
Driving Forces:-Why Noc Approach is needed?Single Chip embeded systems such as IBM's cell and those used in HDTV are becoming increasingly complex. Such Soc have many cores which perform distinct function, DSP, graphics etc and operate at different clock frequencies. This complicates on chip communication. For example, if no. of cores on a processor increases, then number of potential communication paths between them rises exponentially and with more components, a single bus must address communication over a larger area, which leads to latency.
Typically, chip makers have tried to segment buses for use with different elements on Socs. This process turns buses from being long wires that are globally clocked and stretch the entire length of chip to shorter segments of locally clocked bundled wires connected to bridges at each end.
However, segmenting buses is different for complex Soc and multicore chips. Buses must be manually designed with different segments that suit specific chip architectures. This can be expensive and time consuming process.
Technical Issues:-As the wires on a chip increases the wires get closer to each other thus contributing to parasitic capacitance. This affects performance.
How it Works:-Some HPC and data n/w processors could benefit from circuit switching Noc techniques. However, the approach does not provide for routing flexibility and thus does not avoid n/w congestion. Therefore, today's NOCs use packet switching.
Packet Switched Systems:-Each core has a NIU or n/w interface unit which packetizes the data. The NIUs of each core and that of external peripherals (which are on the Soc itself) are connected by copper paths to the router (residing on Soc itself). As in telecom systems, Noc technology uses routing algorithms and tables to decide the optimal way to send packets.
Networking Techniques:-On chip communication must be very fast,latency free and flexible. Thus, the n/w techniques must be simple. The trade off is that simple network offers fewer capabilities.
- TCP/IP entails too much latency and wouldn't be helpful.
- Open core protocol international partnership thus developed the OCP standard for on chip communications with which some NOC vendors work.
Architectures and Topologies
It depends and changes from chip to chip.
Mesh NOC topology :- Used where high degree of parallelism required. Well suited for multiprocessor Socs whoose core must run in parallel. Used in Technion univ Israel.
Clustered Mesh:- BONE (Basic on chip network) developed by Korea Advanced institute of Science and Technology.
Flat Tree topology:- SPIN of Piere & Marie Curie university.
Advantages:-
- Processor cores can focus on processing rather than inter-core communication.
- Nocs work with multiple routers or switches connected by shorter wires, so they are more energy efficient.
- Shorter connections reduce complexity of designing wires to yield predictable speed, power,noise and reliability..
Performance:-
Noc Solution makes chips perform three times as fast as they would be using conventional bus system.
Commercial implementations:-
ST microelectronics designs and produces its own system VSTNOC which company uses in its chips including those for HDTV.
About 300 million Socs that use sonics Inc SMART interconnects NOC technology appear in laptops, PC's, HDTVs, Smart Phones, Gaming consoles etc.
Companies also provide tools that manufacturers can use to incorporate and customize NOCs within their chip designs. For Ex: Alteris provides assemblers, compilers, component libraries, traffic analyzers and simulators. Texas instruments is using them in its OMAP4 family of mobile processors.
FUTURE:
During next five years, NOC adoption will expand to application such as Symmetric Multi Processing (SMP), ASIC, FPGA and internet routers.
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